CMOS scaling is close to dead and that’s been a very special tech and tech enabler. It’s not the only way to continue ramping performance and function. See GPUs for example. But it’s hard to replace that kind of tech.
Because the pitch on wires hasn’t decreased nearly as fast as effective feature size, there’s a strong bottleneck effect that limits single-socket devices in terms of their usable compute power. A good rule of thumb since ~2012, and for at least the next 5 years would be ~12 tera-single-channel ops/sec.
